1. Field
Aspects of the present disclosure relate generally to the field of electronic devices, and more particularly, to circuit analysis techniques.
2. Background
As technology scaling progresses, the costs are increasing. Three dimensional (3D) technology based on through vias can significantly improve circuit performance and density. However, heat dissipation is a major challenge. Because of stacking and/or circuit density, there is a large temperature variation across the chip which may produce extensive localized heating. Device electrical parameters, such as resistance, capacitance, carrier mobility, threshold voltage, electromigration, and sub-threshold leakage current, are all functions of temperature. Thus, a need exists for identifying and quantifying the temperature variation. Similarly, because carrier mobility is a function of stress, a need also exists for identifying and quantifying the stress variation.
Conventionally, temperature variation and stress variation across the chip area are not considered during the circuit design process. For example, timing and power analysis are performed without considering the impact of stress. As for temperature, timing and power analysis occurs at pre-defined corners of the chip where the temperature is selected as either a maximum value or a minimum value. That selected value is assumed for all circuits on the chip. As such, the circuits at the regions of thermal or stress hot spots are not properly characterized during design, possibly leading to circuit failure upon manufacture.